// SPDX-License-Identifier: GPL-2.0
/* Copyright( c ) 2009-2014  Realtek Corporation.*/

#include "../wifi.h"
#include "phy_common.h"
#include "../rtl8723ae/reg.h"
#include <linux/module.h>

/* These routines are common to RTL8723AE and RTL8723bE */

u32 rtl8723_phy_query_bb_reg( struct ieee80211_hw *hw,
			     u32 regaddr, u32 bitmask )
{
	struct rtl_priv *rtlpriv = rtl_priv( hw );
	u32 returnvalue, originalvalue, bitshift;

	RT_TRACE( rtlpriv, COMP_RF, DBG_TRACE,
		 "regaddr(%#x), bitmask(%#x)\n", regaddr, bitmask );
	originalvalue = rtl_read_dword( rtlpriv, regaddr );
	bitshift = rtl8723_phy_calculate_bit_shift( bitmask );
	returnvalue = ( originalvalue & bitmask ) >> bitshift;

	RT_TRACE( rtlpriv, COMP_RF, DBG_TRACE,
		 "BBR MASK=0x%x Addr[0x%x]=0x%x\n", bitmask,
		 regaddr, originalvalue );
	return returnvalue;
}
EXPORT_SYMBOL_GPL( rtl8723_phy_query_bb_reg );

void rtl8723_phy_set_bb_reg( struct ieee80211_hw *hw, u32 regaddr,
			      u32 bitmask, u32 data )
{
	struct rtl_priv *rtlpriv = rtl_priv( hw );
	u32 originalvalue, bitshift;

	RT_TRACE( rtlpriv, COMP_RF, DBG_TRACE,
		 "regaddr(%#x), bitmask(%#x), data(%#x)\n", regaddr, bitmask,
		 data );

	if ( bitmask != MASKDWORD ) {
		originalvalue = rtl_read_dword( rtlpriv, regaddr );
		bitshift = rtl8723_phy_calculate_bit_shift( bitmask );
		data = ( ( originalvalue & ( ~bitmask ) ) | ( data << bitshift ) );
	}

	rtl_write_dword( rtlpriv, regaddr, data );

	RT_TRACE( rtlpriv, COMP_RF, DBG_TRACE,
		 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
		 regaddr, bitmask, data );
}
EXPORT_SYMBOL_GPL( rtl8723_phy_set_bb_reg );

u32 rtl8723_phy_calculate_bit_shift( u32 bitmask )
{
	u32 i;

	for ( i = 0; i <= 31; i++ ) {
		if ( ( ( bitmask >> i ) & 0x1 ) == 1 )
			break;
	}
	return i;
}
EXPORT_SYMBOL_GPL( rtl8723_phy_calculate_bit_shift );

u32 rtl8723_phy_rf_serial_read( struct ieee80211_hw *hw,
			       enum radio_path rfpath, u32 offset )
{
	struct rtl_priv *rtlpriv = rtl_priv( hw );
	struct rtl_phy *rtlphy = &( rtlpriv->phy );
	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
	u32 newoffset;
	u32 tmplong, tmplong2;
	u8 rfpi_enable = 0;
	u32 retvalue;

	offset &= 0xff;
	newoffset = offset;
	if ( RT_CANNOT_IO( hw ) ) {
		pr_err( "return all one\n" );
		return 0xFFFFFFFF;
	}
	tmplong = rtl_get_bbreg( hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD );
	if ( rfpath == RF90_PATH_A )
		tmplong2 = tmplong;
	else
		tmplong2 = rtl_get_bbreg( hw, pphyreg->rfhssi_para2, MASKDWORD );
	tmplong2 = ( tmplong2 & ( ~BLSSIREADADDRESS ) ) |
	    ( newoffset << 23 ) | BLSSIREADEDGE;
	rtl_set_bbreg( hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
		      tmplong & ( ~BLSSIREADEDGE ) );
	rtl_set_bbreg( hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2 );
	rtl_set_bbreg( hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
		      tmplong | BLSSIREADEDGE );
	udelay( 120 );
	if ( rfpath == RF90_PATH_A )
		rfpi_enable = ( u8 ) rtl_get_bbreg( hw, RFPGA0_XA_HSSIPARAMETER1,
						 BIT( 8 ) );
	else if ( rfpath == RF90_PATH_B )
		rfpi_enable = ( u8 ) rtl_get_bbreg( hw, RFPGA0_XB_HSSIPARAMETER1,
						 BIT( 8 ) );
	if ( rfpi_enable )
		retvalue = rtl_get_bbreg( hw, pphyreg->rf_rbpi,
					 BLSSIREADBACKDATA );
	else
		retvalue = rtl_get_bbreg( hw, pphyreg->rf_rb,
					 BLSSIREADBACKDATA );
	RT_TRACE( rtlpriv, COMP_RF, DBG_TRACE,
		 "RFR-%d Addr[0x%x]=0x%x\n",
		 rfpath, pphyreg->rf_rb, retvalue );
	return retvalue;
}
EXPORT_SYMBOL_GPL( rtl8723_phy_rf_serial_read );

void rtl8723_phy_rf_serial_write( struct ieee80211_hw *hw,
				 enum radio_path rfpath,
				 u32 offset, u32 data )
{
	u32 data_and_addr;
	u32 newoffset;
	struct rtl_priv *rtlpriv = rtl_priv( hw );
	struct rtl_phy *rtlphy = &( rtlpriv->phy );
	struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];

	if ( RT_CANNOT_IO( hw ) ) {
		pr_err( "stop\n" );
		return;
	}
	offset &= 0xff;
	newoffset = offset;
	data_and_addr = ( ( newoffset << 20 ) | ( data & 0x000fffff ) ) & 0x0fffffff;
	rtl_set_bbreg( hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr );
	RT_TRACE( rtlpriv, COMP_RF, DBG_TRACE,
		 "RFW-%d Addr[0x%x]=0x%x\n",
		 rfpath, pphyreg->rf3wire_offset,
		 data_and_addr );
}
EXPORT_SYMBOL_GPL( rtl8723_phy_rf_serial_write );

long rtl8723_phy_txpwr_idx_to_dbm( struct ieee80211_hw *hw,
				  enum wireless_mode wirelessmode,
				  u8 txpwridx )
{
	long offset;
	long pwrout_dbm;

	switch ( wirelessmode ) {
	case WIRELESS_MODE_B:
		offset = -7;
		break;
	case WIRELESS_MODE_G:
	case WIRELESS_MODE_N_24G:
		offset = -8;
		break;
	default:
		offset = -8;
		break;
	}
	pwrout_dbm = txpwridx / 2 + offset;
	return pwrout_dbm;
}
EXPORT_SYMBOL_GPL( rtl8723_phy_txpwr_idx_to_dbm );

void rtl8723_phy_init_bb_rf_reg_def( struct ieee80211_hw *hw )
{
	struct rtl_priv *rtlpriv = rtl_priv( hw );
	struct rtl_phy *rtlphy = &( rtlpriv->phy );

	rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
	rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
	rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
	rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;

	rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
	rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
	rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
	rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;

	rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
	rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;

	rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
	rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;

	rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
	    RFPGA0_XA_LSSIPARAMETER;
	rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
	    RFPGA0_XB_LSSIPARAMETER;

	rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = RFPGA0_XAB_RFPARAMETER;
	rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = RFPGA0_XAB_RFPARAMETER;
	rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = RFPGA0_XCD_RFPARAMETER;
	rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = RFPGA0_XCD_RFPARAMETER;

	rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
	rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
	rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
	rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;

	rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
	rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;

	rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
	rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;

	rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
	rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
	rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
	rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;

	rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
	rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
	rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
	rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;

	rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
	rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
	rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
	rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;

	rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;
	rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;
	rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBANLANCE;
	rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;

	rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
	rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
	rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
	rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;

	rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE;
	rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;
	rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;
	rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE;

	rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
	rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
	rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
	rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;

	rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
	rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
	rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;
	rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;

	rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK;
	rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK;

}
EXPORT_SYMBOL_GPL( rtl8723_phy_init_bb_rf_reg_def );

bool rtl8723_phy_set_sw_chnl_cmdarray( struct swchnlcmd *cmdtable,
				      u32 cmdtableidx,
				      u32 cmdtablesz,
				      enum swchnlcmd_id cmdid,
				      u32 para1, u32 para2,
				      u32 msdelay )
{
	struct swchnlcmd *pcmd;

	if ( cmdtable == NULL ) {
		WARN_ONCE( true, "rtl8723-common: cmdtable cannot be NULL.\n" );
		return false;
	}

	if ( cmdtableidx >= cmdtablesz )
		return false;

	pcmd = cmdtable + cmdtableidx;
	pcmd->cmdid = cmdid;
	pcmd->para1 = para1;
	pcmd->para2 = para2;
	pcmd->msdelay = msdelay;
	return true;
}
EXPORT_SYMBOL_GPL( rtl8723_phy_set_sw_chnl_cmdarray );

void rtl8723_phy_path_a_fill_iqk_matrix( struct ieee80211_hw *hw,
					bool iqk_ok,
					long result[][8],
					u8 final_candidate,
					bool btxonly )
{
	u32 oldval_0, x, tx0_a, reg;
	long y, tx0_c;

	if ( final_candidate == 0xFF ) {
		return;
	} else if ( iqk_ok ) {
		oldval_0 = ( rtl_get_bbreg( hw, ROFDM0_XATXIQIMBALANCE,
					  MASKDWORD ) >> 22 ) & 0x3FF;
		x = result[final_candidate][0];
		if ( ( x & 0x00000200 ) != 0 )
			x = x | 0xFFFFFC00;
		tx0_a = ( x * oldval_0 ) >> 8;
		rtl_set_bbreg( hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a );
		rtl_set_bbreg( hw, ROFDM0_ECCATHRESHOLD, BIT( 31 ),
			      ( ( x * oldval_0 >> 7 ) & 0x1 ) );
		y = result[final_candidate][1];
		if ( ( y & 0x00000200 ) != 0 )
			y = y | 0xFFFFFC00;
		tx0_c = ( y * oldval_0 ) >> 8;
		rtl_set_bbreg( hw, ROFDM0_XCTXAFE, 0xF0000000,
			      ( ( tx0_c & 0x3C0 ) >> 6 ) );
		rtl_set_bbreg( hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000,
			      ( tx0_c & 0x3F ) );
		rtl_set_bbreg( hw, ROFDM0_ECCATHRESHOLD, BIT( 29 ),
			      ( ( y * oldval_0 >> 7 ) & 0x1 ) );
		if ( btxonly )
			return;
		reg = result[final_candidate][2];
		rtl_set_bbreg( hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg );
		reg = result[final_candidate][3] & 0x3F;
		rtl_set_bbreg( hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg );
		reg = ( result[final_candidate][3] >> 6 ) & 0xF;
		rtl_set_bbreg( hw, 0xca0, 0xF0000000, reg );
	}
}
EXPORT_SYMBOL_GPL( rtl8723_phy_path_a_fill_iqk_matrix );

void rtl8723_save_adda_registers( struct ieee80211_hw *hw, u32 *addareg,
				 u32 *addabackup, u32 registernum )
{
	u32 i;

	for ( i = 0; i < registernum; i++ )
		addabackup[i] = rtl_get_bbreg( hw, addareg[i], MASKDWORD );
}
EXPORT_SYMBOL_GPL( rtl8723_save_adda_registers );

void rtl8723_phy_save_mac_registers( struct ieee80211_hw *hw,
				    u32 *macreg, u32 *macbackup )
{
	struct rtl_priv *rtlpriv = rtl_priv( hw );
	u32 i;

	for ( i = 0; i < ( IQK_MAC_REG_NUM - 1 ); i++ )
		macbackup[i] = rtl_read_byte( rtlpriv, macreg[i] );
	macbackup[i] = rtl_read_dword( rtlpriv, macreg[i] );
}
EXPORT_SYMBOL_GPL( rtl8723_phy_save_mac_registers );

void rtl8723_phy_reload_adda_registers( struct ieee80211_hw *hw,
				       u32 *addareg, u32 *addabackup,
				       u32 regiesternum )
{
	u32 i;

	for ( i = 0; i < regiesternum; i++ )
		rtl_set_bbreg( hw, addareg[i], MASKDWORD, addabackup[i] );
}
EXPORT_SYMBOL_GPL( rtl8723_phy_reload_adda_registers );

void rtl8723_phy_reload_mac_registers( struct ieee80211_hw *hw,
				      u32 *macreg, u32 *macbackup )
{
	struct rtl_priv *rtlpriv = rtl_priv( hw );
	u32 i;

	for ( i = 0; i < ( IQK_MAC_REG_NUM - 1 ); i++ )
		rtl_write_byte( rtlpriv, macreg[i], ( u8 ) macbackup[i] );
	rtl_write_dword( rtlpriv, macreg[i], macbackup[i] );
}
EXPORT_SYMBOL_GPL( rtl8723_phy_reload_mac_registers );

void rtl8723_phy_path_adda_on( struct ieee80211_hw *hw, u32 *addareg,
			      bool is_patha_on, bool is2t )
{
	struct rtl_hal *rtlhal = rtl_hal( rtl_priv( hw ) );
	u32 pathon;
	u32 i;

	if ( rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE ) {
		pathon = is_patha_on ? 0x04db25a4 : 0x0b1b25a4;
		if ( !is2t ) {
			pathon = 0x0bdb25a0;
			rtl_set_bbreg( hw, addareg[0], MASKDWORD, 0x0b1b25a0 );
		} else {
			rtl_set_bbreg( hw, addareg[0], MASKDWORD, pathon );
		}
	} else {
		/* rtl8723be */
		pathon = 0x01c00014;
		rtl_set_bbreg( hw, addareg[0], MASKDWORD, pathon );
	}

	for ( i = 1; i < IQK_ADDA_REG_NUM; i++ )
		rtl_set_bbreg( hw, addareg[i], MASKDWORD, pathon );
}
EXPORT_SYMBOL_GPL( rtl8723_phy_path_adda_on );

void rtl8723_phy_mac_setting_calibration( struct ieee80211_hw *hw,
					 u32 *macreg, u32 *macbackup )
{
	struct rtl_priv *rtlpriv = rtl_priv( hw );
	u32 i = 0;

	rtl_write_byte( rtlpriv, macreg[i], 0x3F );

	for ( i = 1; i < ( IQK_MAC_REG_NUM - 1 ); i++ )
		rtl_write_byte( rtlpriv, macreg[i],
			       ( u8 ) ( macbackup[i] & ( ~BIT( 3 ) ) ) );
	rtl_write_byte( rtlpriv, macreg[i], ( u8 ) ( macbackup[i] & ( ~BIT( 5 ) ) ) );
}
EXPORT_SYMBOL_GPL( rtl8723_phy_mac_setting_calibration );

void rtl8723_phy_path_a_standby( struct ieee80211_hw *hw )
{
	rtl_set_bbreg( hw, 0xe28, MASKDWORD, 0x0 );
	rtl_set_bbreg( hw, 0x840, MASKDWORD, 0x00010000 );
	rtl_set_bbreg( hw, 0xe28, MASKDWORD, 0x80800000 );
}
EXPORT_SYMBOL_GPL( rtl8723_phy_path_a_standby );

void rtl8723_phy_pi_mode_switch( struct ieee80211_hw *hw, bool pi_mode )
{
	u32 mode;

	mode = pi_mode ? 0x01000100 : 0x01000000;
	rtl_set_bbreg( hw, 0x820, MASKDWORD, mode );
	rtl_set_bbreg( hw, 0x828, MASKDWORD, mode );
}
EXPORT_SYMBOL_GPL( rtl8723_phy_pi_mode_switch );
